The present disclosure is generally related to a semiconductor device, and specifically to a semiconductor device having improved edge trench, source electrode and gate electrode structures.
A typical power semiconductor die has an active area where an array of mesas and trenches that implement the device are located, a field termination area around the active area, and an inactive area where interconnects and channel stops may be provided. The field termination area minimizes the electric fields around the active area. The breakdown voltage of the device may be determined by the breakdown processes associated with the active area. However various passive breakdown processes can occur in the field termination area and inactive area at significantly lower voltages. Many designs often require compromises that increase the total die area and cost of the die. A background example may be shown in U.S. Patent Application Publication No. 2010/0140696 (“Patent Literature 1”).
In an edge trench, a shield electrode may be formed in which a thickness of an insulating layer facing to an epitaxial side is larger than that in other trenches. Such a design may provide a high withstand voltage. However, problems may arise in that, while higher withstand voltages are desirable, the ability to endure fractures that may occur within the edge trench must be addressed.